Cyclic convolution is also known as circular convolution. It is simpler to compute and produces less output samples compared to linear convolution. Given x(n)and h(n), the length - N cyclic convolution can be expressed as where (n-K) mod N returns the remainder of the integer division of n-k by N. There are many architectures for calculating cyclinc convolution of any two signals. Implementation using Fermat Number Transform (FNT) is one of them. Fermat
Number is a positive integer of the form Fn = 22n +1 where n is a nonnegative integer. The basic property of FN is that they are recursive. This paper presents a high speed parallel architecture for cyclic convolution based on Fermat Number Transform (FNT) in the diminished-1 number system. A code conversion method without addition (CCWA) and a butterfly operation method without addition (BOWA) are proposed to perform the FNT and its inverse (IFNT) except their final stages in the convolution. The point wise multiplication in the convolution is accomplished by modulo 2n+1 partial product multipliers (MPPM) and output partial products which are inputs to the IFNT. Thus modulo 2n+1 carry propagation additions are avoided in the FNT and the IFNT except their final stages and the modulo 2n+1 multiplier. The execution delay of the parallel architecture is reduced evidently to the decrease of modulo 2n +1 carry-propagation addition.
General Terms
This paper studying parallel architecture design for various applications in VLSI Design, for high speed data transformation, using Fermat number transform, different designing method to provide high speed data transmission.
Keywords: VLSI, DSP, FPGA Implementation using Verilog and VHDL coding method. Tools are Xilinx new version |