This paper presents the ultra low power synchronous counter using carbon nanotube Field Effect Transistor. The proposed counter is designed using 18 nm technology. The counter is designed using T flip flop. Proposed design minimizes the power consumption and operating voltage. As far as it is known, this is the first attempt to design synchronous counter using CNTFET. Results of the design are compared with CMOS technology based synchronous counter. This paper also presents design and simulation of T flip flop.