Low power consumption and smaller area are the most important criteria for the fabrication of DSP systems. Optimizing speed and power of the multiplier is a major design issue. However, speed and power are usual constraints conflicting to each other, so that increasing speed results in larger areas. Parallel multipliers like Braun’s multiplier are preferred over serial multipliers as they consume more power. In this paper, we have designed a low power FIR filter, by simplification of addition operation in a bypassing multiplier. The same has been implemented and the power dissipation is calculated. The effectiveness of the proposed technique is also proved by comparing the obtained results with the existing low power FIR filter design.
 

Keywords – Braun’s multiplier, Bypassing multiplier, FIR filter, FPGA.