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TITLE : DESIGN OF LOW POWER 2-D MULTIPLIER USING 2-D BYPASSING TECHNIQUE  
AUTHORS : Vinod Kumar D      Krishnamacharya C      Gangaraju B      Uma Maheswara Rao K.V., Avinash K  
DOI : http://dx.doi.org/10.18000/ijies.30130  
ABSTRACT :

Based on the simplification of the addition operations in a low-power bypassingbased multiplier, a low-cost low-power bypassingbased multiplier is proposed. Compared with rowbypassing multiplier, column-bypassing multiplier and 2-dimensional bypassing-based multiplier for 20 tested examples, the experimental results show that our proposed low-cost low power multiplier saves 15.1% of hardware cost and reduces 29.6% of the power dissipation on the average for 4x4, 8x8 and 16x16 multipliers.

 
Keywords— Row bypassing multiplier, Column bypassing multiplier, 2-dimensional bypassing multiplier, and power dissipation.
 
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