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TITLE : VLSI ARCHITECTURE OF DECISION BASED MODIFIED SELECTION SORT FILTER FOR SALT AND PEPPER NOISE REMOVAL  
AUTHORS : Vasanth K                 
DOI : http://dx.doi.org/10.18000/ijies.30131  
ABSTRACT :

A Novel architecture is proposed for the decision based modified selection sorting. The need for an optimized area, speed and power plays a vital role for any VLSI implementation of image processing hardware. The proposed architecture checks the given pixel is noisy or not and finds the median only if it is noisy. Under high noisy conditions the computed median might also be noisy hence arithmetic mean of uncorrupted pixels in the current window or replacement of neighborhood pixel over the processed pixel is done. The proposed architecture is compared with other decision based median finding architecture on the basis of power, speed, and area. The proposed architecture is targeted to Spartan 3e Device with gate capacity 5000 using Xilinx 7.1 i compiler version. The proposed scheme is capable of operating at 233.318MHz requiring 2800 number of slices with a power dissipation of 100mw.

 
Keywords—Decision based median filters, modified selection sorting, salt and pepper noise
 
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