Background: Semiconductor industry has achieved almost exponential scaling down in feature size and has no 100% solution in leakage current in CMOS. To replace CMOS technology, researchers done at nanoscale in recent years. Among emerging technologies, QCA plays an important role. QCA can implement digital circuits with high speed, small size and reduced power consumption. Our aim is on designing of different types of adder circuits in QCA.

Objective: Our objective is to minimize the area, latency and also the number of cells in adder circuits in QCADesigner.

Results: The proposed design reduces the number of cells and area compared with the available structures. By using QCA cells, different types of adders were designed Then they were simulated using QCADESIGNER tool. The performance can be analysed with the number of clock cycles.

Conclusion: Experimental results show that the performances of proposed design of adders are more efficient than conventional designs.