The dynamic power dissipation is the dominant source of power dissipation inCMOScircuits. It is directly related to the number of signal transitions and glitches. The glitches occupy a considerable amount of power of the total power dissipation in CMOS circuits. This paper presents a survey of the different techniques used for decreasing the dynamic power by reduction of glitches. The advantages and limitations of these techniques are also discussed.

Key words: Glitches,CMOScircuits, low power, path balancing, gate sizing.