This paper presents a 32-bit multiply-accumulator (MAC) architecture capable of supporting multiple precisions. The MAC architecture is multiplexing into the partial product generation and by inserting partial product in the carry chain of the reduction tree and the final carry-propagate adder. This Switching Power Swiftness Improvement Technique (SPSIT) has been applied on both the compression tree of the multipliers and the modified Booth Encoder to enlarge the power swiftness, for high-speed and low-power purposes. To filter out the spurious switching power of the MAC unit, there are two approaches, i.e., using registers and using AND gates, to assert the data signals of LP multipliers after the data transition has been proposed. The SPSIT approach leads to a 40% power consumption reduction and speed improvement when compared with the other power minimization technique. This is an example of “shared segmentation” in which the existing scalar structure is segmented and then shared between vector modes. The MAC is area efficient, which makes it suitable for high-performance processors and, possibly, dynamically reconfigurable processors. High-speed arithmetic, data-path design, VLSI, MAC, multiply-accumulate, multiplier, vector, modified Booth,

Key words: Wallace, signed, unsigned, integer, fixed-point.