This paper investigates a Low-Density Parity-Check (LDPC) coded rthogonal Frequency-Division Multiplexing (OFDM) wireless communication system based on IEEE 802.11a standard. This paper studies low-complexity high speed decoder architectures for quasi-cyclic low density parity check (QC-LDPC) codes. Algorithmic transformation and architectural level optimization are incorporated to reduce the critical path and bit error rate (BER). Enhanced partially parallel decoding architectures are proposed to linearly increase the throughput of conventional partially parallel decoders through introducing a small percentage of extra hardware. The LDPC decoding procedure is simplified without the estimation of channel noise power. Simulation results show that this algorithm is effective and the decoding performance is satisfied when maximum iteration number is 10.

Key words: IEEE 802.11a standard; LDPC coded; quasi-cyclic (QC) codes; Modulation; OFDM system; decoding