In this paper a programmable clock multiplier based on Delay Locked Loop (DLL) is proposed. It does not require any L-C tank circuit or ring oscillator. Although it requires a clean reference signal it has several advantages over conventional Phase Locked Loop (PLL) based clock multiplication in terms of stability, power consumption, jitter performance and ease to design. The operating frequency range of DLL is 170 MHz to 252 MHz. The proposed clock multiplier is programmable with multiplication factor of 1X, 2X, 4X and hence can generate clock of frequency range 170 MHz to 1 GHz with 50 % duty cycle. The proposed circuit is simulated in SPICE at 180 nm technology node and 1.8 V power supply with a reference signal of 200 MHz and output signal is shown with various multiplication factor. The power consumption in each case is less than 10 mw.