With continuous advancements in technologies, the SRAM memories have undergone changes with respect to decrease in geometric cell size, increased transistor density and high frequency. Such circuits consume an excessive amount of power. In this paper the power analysis of a conventional 6T SRAM cell is carried out in 90 nm process technology. The power dissipation of the SRAM cell during read, write operations and in standby mode are observed and then transistor stacking is applied to the inverters in the SRAM cell. The simulations are done at various supply voltages from 0.7 v to 1.0 v. Simulation results show much reduction in standby power dissipation after the application of stacking technique to the SRAM circuit. The circuits have been simulated using HSPICE with BSIM4 MOSFET models.