Reversible circuits avoids energy loss. Hence such circuits have significant potential in futuristic technologies such as ultra low power VLSI circuits, quantum computing, optical information processing, bioinformatics, and nanotechnology. In this paper, a reversible design of a single precision floating point multiplier is proposed. 24 x 24 bit multiplier is required to multiply the significand of the floating point numbers. This multiplier is constructed using operand decomposition approach. Minimization of quantum cost and garbage output is considered as optimization criteria. Quantum cost of a reversible gate represents its computational complexity. Garbage outputs are unutilized outputs that are not used as primary outputs and which cannot be used as inputs for new computation. The reversible partial product generation circuitry, the reversible half adder and full adder and reversible 4:2 compressor for use in the compression tree, the reversible conditional right-shifter for normalization of the product are carefully designed and comparison with earlier designs shows the improvement in quantum cost and garbage output.