One of the important most generally used frequency synthesizer is based on the Phase Locked Loop, which is a building block of the transceiver. Carrier generation can be performed by the frequency synthesizer and it is used for up/down conversion operations. Conversion operation is also a critical block in transceiver, due to the operations carry out at high frequency, takes a huge portion of the entire power consumption on the transceiver side. The main objective of this paper is to design a critical block for frequency synthesizer with minimal power consumptions. Here the proposed design includes XOR PD, Low power LPF, Low power VCO and Parabolic correction blocks which give low power utilization with high accuracy and a reduction in the complexity of the system in terms of hardware and memory usage.

We can achieve better performance from this architecture in terms of low power. The proposed PLL synthesizer is simulated in MATLAB software and the results are shown that the power utilization is very less than the existing approaches.

Keywords: Frequency Synthesizer, Phase Lock Loop, CMOS, Transceiver in Wireless Networks