In recent years, Elliptic curve cryptography has gained widespread exposure and acceptance and has already been included in many security standards. Engineering of ECC is a complex, interdisciplinary research field encompassing such as Mathematics, Computer Science and Electrical Engineering. ASIP-based implementations constitute a key trend in SoC design enabling optimal tradeoffs between performance and flexibility. This paper details the design of a High speed pipelined ASIP processor for ECC using FPGAtechnology. Aseven stage pipeline has been applied to the design, and pipeline stalls are avoided via instruction reordering and data forwarding. Three complex instructions are introduced to reduce the latency by reducing the overall number of instructions.The architecture was programmed in Verilog and synthesized to Xilinx Vertex II Pro devices .Simulation was done with Modelsim XE 6.1 e, VLSI simulation software from Mentor Graphics Corporation especially forXilinx devices.

Keywords: FPGA, Elliptic Curve Cryptography, ASIP